1. Field of the Invention
The present invention generally relates to systems and methods for inspecting an edge of a specimen. Certain embodiments relate to a system that includes an illumination subsystem that is configured to direct light to the edge of the specimen at an oblique angle of incidence.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a specimen such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Wafers may contain defects both in central regions of the wafers as well as in edge regions, which include a relatively narrow region around the periphery of the wafers, and the edges of the wafers. Examples of defects that may be found in the edge region and on the edge of wafers include, but are not limited to, chips, cracks, scratches, marks, particles, and residual chemicals (e.g., resist and slurry). As wafer sizes continue to increase, both wafer and integrated circuit (IC) manufacturers are becoming more concerned about defectivity at or near the wafer edge. The main concerns are that edge defects could fall onto the central part of the wafer thereby causing untraceable yield loss, cross contamination during processing, and/or catastrophic wafer breakage. These yield loss mechanisms are experienced by most wafer and IC manufacturers at one time or another.
Traditionally, wafer inspection tools are designed to inspect a central region of the wafers (i.e., a surface of the wafer on which electrical elements will be formed or a surface of the wafer opposite that on which electrical elements will be formed). Since these areas of the wafer reflect or scatter relatively small amounts of light, such wafer inspection tools are designed to detect relatively small amounts of light. However, near the edge of the wafer, relatively large amounts of light may be reflected or scattered from the wafer due to edge features such as a bevel formed in the edge. As a result, these large amounts of light will saturate the detectors of traditional wafer inspection systems. Consequently, any output signals generated near or at the edge of wafers by such wafer inspection tools are generally unusable. In some instances, the wafer inspection systems may be designed to block light from reaching the detectors when inspecting near the edge of the wafer to protect the detectors from damage that may be caused by the relatively high intensity light.
Edge inspection of specimens may be currently performed manually by visual (unaided human eye) inspection with incoherent light sources or by visual inspection aided by manual or automated wafer-handling light microscopy. However, some edge inspection systems have been developed to detect defects at or near the edge of wafers. Some edge inspection systems use digital microscopic image acquisition with a plurality of imaging devices and incoherent or coherent illumination to image different edge regions of a semiconductor wafer with computer processing of the images by a defect detection and classification algorithm. Additional examples of apparatuses for detecting defects along the edge of electronic media such as semiconductor wafers are illustrated in U.S. Patent Application Publication Nos. 2003/0030050 by Choi and 2003/0030795 by Swan et al., which are incorporated by reference as if fully set forth herein.
Due to the substantially different reflecting and scattering characteristics of the edge of wafers in comparison to the central region of the wafer, such edge inspection systems have substantially different configurations than traditional wafer inspection tools. Therefore, the edge inspection systems are not optimized to, or even able to, detect defects in the central region of the wafers. Consequently, if wafer or IC manufacturers want to detect defects in both the central and outer regions of wafer (as is usually the case since defects in either region may result in expensive yield losses and other problems), they will need to purchase two separate tools. For example, edge inspection may be performed using an additional stand alone inspection tool or an additional subsystem on an existing inspection tool.
Using two different wafer inspection tools instead of just one inspection tool will obviously increase costs in many ways such as increases in clean room real estate costs, operating costs, tool maintenance costs, and reduced throughput. However, since most inspection tools are not capable of inspecting both the inner region and edge of wafers, and due to the increasing costs associated with defect-based yield losses, wafer and IC manufacturers may not be able to avoid the costs associated with multiple, different inspection tools. In addition, incorporating an additional subsystem into an existing inspection tool will also increase the overall cost of the tool due to the hardware and possibly software required for the additional inspection subsystem and increased maintenance costs for the additional subsystem.
Accordingly, it may be advantageous to develop systems and methods for inspecting an edge of a specimen that are capable of inspecting the entire edge of the specimen, including the top bevel, the apex, and the bottom bevel, and can be implemented on an existing inspection system with relatively inexpensive changes to the configuration of the existing inspection system.